View CRD4525-Q1_1273545.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

copyright ? cirrus logic, inc. 2008 (all rights reserved) http://www.cirrus.com advance product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 30 w quad half-bridge digital amplifier power stage features ? configurable outputs (10% thd+n) ? 2 x 15 w into 8 ? , full-bridge ? 1 x 30 w into 4 ? , parallel full-bridge ? 4 x 7.5 w into 4 ? , half-bridge ? 2 x 7.5 w into 4 ? , half-bridge + 1 x 15 w into 8 ? , full-bridge ? space-efficient the rmally-enhanced qfn ? no external heat sink required ? > 100 db dynamic range - system level ? < 0.1% thd+n @ 1 w - system level ? built-in protection with error reporting ? over-current ? thermal warning and overload ? under-voltage ? +8 v to +18 v high voltage supply ? pwm popguard ? technology for quiet startup ? no bootstrap required ? low quiescent current ? low power standby mode common applications ? integrated digital televisions ? portable media player docking stations ? mini/micro shelf systems ? powered desktop speakers general description the cs4412a is a high-efficiency power stage for digital class-d amplifiers designed to input pwm signals from a modulator such as the cs4525. the power stage out- puts can be configured as four half-bridge channels, two half-bridge channels and one full-bridge channel, two full-bridge channels, or one parallel full-bridge channel. the cs4412a integrates on-chip over-current, under- voltage, over-temperature protection, and error report- ing as well as a thermal wa rning indicator. the low r ds(on) outputs can source up to 2.5 a peak current, delivering high efficiency which allows small device package and lower power supplies. the cs4412a is available in a 48-pin qfn package in commercial grade (-10c to +70c). the crd4412a customer reference design is also available. please re- fer to ?ordering information? on page 23 for complete ordering information. vp amplifier out 1 amplifier out 2 pgnd amplifier out 3 amplifier out 4 gate drive gate drive gate drive gate drive 2.5 v to 5 v 8 v to 18 v in 1 non-overlap time insertion non-overlap time insertion non-overlap time insertion non-overlap time insertion protection & error reporting in 2 in 3 in 4 current & thermal data control logic hardware configuration reset mode configuration jun '08 ds786a2 cs4412a
2 ds786a2 cs4412a table of contents 1. pin description ............................................................................................................ ..................... 3 2. characteristics and specificat ions .......... ................. ................ ................ ................ ........... 5 recommended operating conditions .................................................................................... 5 absolute maximum ratings ...................................................................................................... .. 5 pwm power output characteristics ..................................................................................... 6 dc electrical characteristics ................................................................................................ 7 digital interface specifications .............. ................ ................ ................. ................ .............. 7 digital i/o pin characteristics ............................................................................................... .. 8 3. typical connection diagrams .............................................................................................. ... 9 4. applications ............................................................................................................... .................... 13 4.1 overview .................................................................................................................. ...................... 13 4.2 reset and power-up ........................................................................................................ .............. 13 4.2.1 pwm popguard transient control ........................................................................................ 13 4.2.2 initial pulse edge delay ................................................................................................ ........ 14 4.2.3 recommended po wer-up sequence .................................................................................... 14 4.2.4 recommended po wer-down sequence ......................... ...................................................... 14 4.3 output mode configuration ................................................................................................. ........... 15 4.4 output filters ............................................................................................................ ..................... 16 4.4.1 half-bridge output filter ............................................................................................... ......... 16 4.4.2 full-bridge output filter (s tereo or parallel) ......................................................................... 1 8 4.5 device protection and error reporting ..................................................................................... ..... 19 4.5.1 over-current protection ................................................................................................. ....... 19 4.5.2 thermal warning, thermal er ror, and under-volta ge error ................................................. 19 5. power supply, grounding, and pcb layout ....................................................................... 20 5.1 power supply and grounding ................................................................................................ ........ 20 5.1.1 integrated vd regulator ................................................................................................. ....... 20 5.2 qfn thermal pad ........................................................................................................... ............... 20 6. parameter definitions ...................................................................................................... .......... 21 7. package dimensions ......................................................................................................... ........... 22 8. thermal characteristics .................................................................................................... ..... 23 8.1 thermal flag .............................................................................................................. .................... 23 9. ordering information ....................................................................................................... ......... 23 10. revision history .......................................................................................................... ................ 23 list of figures figure 1.stereo full-bridge typi cal connection diagram ........................................................................ ... 9 figure 2.2.1 channel typical con nection diagram ............................................................................... ... 10 figure 3.4 channel half-bridge typical connection diagram .................................................................. 11 figure 4.parallel full-brid ge typical connection diagram ...................................................................... .12 figure 5.output filter - half-bridge .............. ............................................................................ ................. 16 figure 6.output filter - full-bridge ............... ........................................................................... .................. 18 list of tables table 1. i/o power rails ....................................................................................................... ....................... 8 table 2. typical ramp times for typical vp voltages ............................................................................ .. 13 table 3. output mode configuration options...... ............................................................................... ........ 15 table 4. low-pass filter componen ts - half-bridge.............................................................................. .... 16 table 5. dc-blocking capacitors values - half-bridge........................................................................... ... 17 table 6. low-pass filter components - full-bridge .............................................................................. .... 18 table 7. over-current error conditions ......................................................................................... ............ 19 table 8. thermal and under-volta ge error conditions............................................................................ .. 19 table 9. power supply configuration and settings. .............................................................................. ..... 20
ds786a2 3 cs4412a 1. pin description pin name pin # pin description cnfg0 cnfg1 cnfg2 1 2 3 out configuration select ( input ) - used to set the pwm output configuration mode. see ?output mode configuration? on page 15 . in1 in2 in3 in4 4 5 6 7 pwm input ( input ) - logic-level switching inputs from a pwm modulator. rst12 rst34 8 46 reset input ( input ) - reset inputs for channels 1/2 and 3/4, respectively. active low. lvd 9 vd voltage level indicator ( input ) - identifies the voltage level attached to vd. when applying 5.0 v to vd, lvd must be connected to vd. when applying 2.5 v or 3.3 v to vd, lvd must be gnd. vd_reg 11 core digital power ( output ) - internally generated low voltage power supply for digital logic. vd 12 digital power ( input ) - positive power supply for the internal regulators and digital i/o. ocref 21 over-current reference ( input ) - sets over-current trigger level. connect pin through a resistor to gnd. see ?device protection and error reporting? on page 19 . this pin should not be left float- ing. top-down (through package) view 48-pin qfn package 12 7 6 5 4 3 2 1 11 10 9 8 25 30 31 32 33 34 35 36 26 27 28 29 14 13 15 16 17 18 19 20 21 22 23 24 47 48 46 45 44 43 42 41 40 39 38 37 gnd gnd rst34 ramp erroc34 erroc12 twr gnd gnd gnd gnd cnfg0 cnfg1 cnfg2 in1 in2 rst12 vp out1 pgnd pgnd out2 vp vp out3 lvd vd_reg vd pgnd pgnd pgnd pgnd pgnd pgnd out4 vp ocref pgnd pgnd ramp_cap erruvte in3 in4 gnd gnd gnd gnd gnd thermal pad
4 ds786a2 cs4412a ramp_cap 24 output ramp capacitor ( input ) - used by the pwm popguard transient control to suppress the initial pop in half-bri dge-configured outputs. gnd 10,13 14,15 16,17 18,19 20,47 48 ground ( input ) - ground for the internal logic and i/o. these pins should be connected to the common system ground. vp 25,30 31,36 high voltage output power ( input ) - high voltage power supply for the individual output power half-bridge devices. pgnd 22,23 27,28 33,34 37,38 39,40 power ground ( input ) - ground for the individual output power half-bridge devices. these pins should be connected to the common system ground. out4 out3 out2 out1 26 29 32 35 pwm output ( output ) - amplified pwm power outputs. twr 41 thermal warning output ( output ) - thermal warning output. open drain, active low. see ?device protection and error reporting? on page 19 . erruvte 42 thermal and under-voltage error output ( output ) - error flag for thermal shutdown and under- voltage. open drain, active low. see ?device protection and error reporting? on page 19 erroc12 erroc34 43 44 over-current error output ( output ) - over-current error flag for the associated outputs. open drain, active low. see ?device protection and error reporting? on page 19 . ramp 45 ramp-up/down select ( input ) - set high to enable ramping. when set low, ramping is disabled. see ?pwm popguard transient control? on page 13 . thermal pad - thermal pad - thermal relief pad for optimized heat dissipation. see ?qfn thermal pad? on page 20 for more information. pin name pin # pin description
ds786a2 5 cs4412a 2. characteristics and specifications recommended operating conditions gnd = pgnd = 0 v, all voltages with respect to ground. absolute maximum ratings gnd = pgnd = 0 v; all voltages with respect to ground. warning: operation beyond these limits may result in perma nent damage to the device. normal operation is not guaranteed at these extremes. notes: 1. any pin except supplies. transien t currents of up to 100 ma on the pwm input pins will not cause scr latch-up. 2. the maximum over/under voltage is limited by the input current. parameters symbol min nom max units dc power supply digital core vd 2.375 2.5 2.625 v vd 3.135 3.3 3.465 v vd 4.75 5.0 5.25 v power stage vp 8.0 18.0 v temperature ambient temperature commercial t a -10 - +70 c junction temperature t j -10 - +125 c parameters symb ol min max units dc power supply power stage outputs switching and under load power stage no output switching digital core vp vp vd -0.3 -0.3 -0.3 19.8 23.0 6.0 v v v inputs input current ( note 1 )i in -10ma digital input voltage ( note 2 )v ind -0.3 vd + 0.4 v temperature ambient operating temper ature - power applied commercial t a -20 +85 c storage temperature t stg -65 +150 c
6 ds786a2 cs4412a pwm power output characteristics test conditions (unless otherwise specified): gnd = pgnd = 0 v; all volt ages with respect to ground; t a = 25c; vd = 3.3 v; vp = 18 v; r l =8 ? for full-bridge, r l =4 ? for half-bridge and parallel full-bridge; pwm switch rate = 384 khz; 10 hz to 20 khz measurement bandwidth; input source is cs4525 pwm_sig outputs; perfor- mance measurements taken with a fu ll-scale 997 hz sine wave, an aes17 meas urement filter; half-bridge mea- surements taken through the half-bridge output filter shown in figure 5 ; stereo full-bridge and parallel full- bridge measurements taken through the full-bridge output filter shown in figure 6 ;. parameters symbol conditions min typ max units power output per channel stereo full-bridge half-bridge parallel full-bridge p o thd+n < 10% thd+n < 1% thd+n < 10% thd+n < 1% thd+n < 10% thd+n < 1% - - - - - - 15 12 7.5 5.5 30 23.5 - - - - - - w w w w w w total harmonic distortion + noise stereo full-bridge half-bridge parallel full-bridge thd+n p o = 1 w p o = 0 dbfs = 11.3 w p o = 1 w p o = 0 dbfs = 5.0 w p o = 1 w p o = 0 dbfs = 22.6 w - - - - - - 0.08 0.10 0.12 0.19 0.1 0.3 - - - - - - % % % % % % dynamic range stereo full-bridge half-bridge parallel full-bridge dyr p o = -60 dbfs, a-weighted p o = -60 dbfs, unweighted p o = -60 dbfs, a-weighted p o = -60 dbfs, unweighted p o = -60 dbfs, a-weighted p o = -60 dbfs, unweighted - - - - - - 102 99 102 97 102 99 - - - - - - db db db db db db mosfet on resistance r ds(on) i d = 0.5 a, t j =50 c - 280 - m ? efficiency h p o = 2 x 15 w, r l = 8 ? -85-% minimum output pulse width pw min no load - 25 - ns rise time of outx t r resistive load - 10 - ns fall time of outx t f resistive load - 5 - ns pwm output over-current error trigger point i ce t a =25 c, ocref = 16.2 k ? t a =25 c, ocref = 18 k ? t a =25 c, ocref = 22 k ? - - - 2.5 2.1 1.7 - - - a a a junction thermal warning trigger point t tw - 105 - c junction thermal error trigger point t te - 125 - c vp under-voltage error falling trigger point v uvfall t a =25 c-4.74.9v vp under-voltage error rising trigger point v uvrise t a =25 c - 4.95 5.4 v
ds786a2 7 cs4412a dc electrical characteristics gnd = pgnd = 0 v; all voltages with respect to ground; pwm switch rate = 384 khz; unless otherwise specified. notes: 3. normal operation is defined as rst12 and rst34 = hi. 4. power-down mode is defined as rst12 and rst34 = low with all input lines held static. 5. power supply current increases wit h increasing pwm switching rates. digital interface specifications gnd = pgnd = 0 v; all voltages with respect to ground; unless otherwise specified. parameters min typ max units normal operation (notes 3 , 5 ) power supply current vd = 3.3 v - 20 - ma power dissipation vd = 3.3 v - 66 - mw power-down mode ( note 4 ) power supply current vd = 3 .3 v - 2 - ma vd_reg characteristics nominal voltage dc current source 2.25 - 2.5 - 2.75 3 v ma parameters symbol min max units high-level input voltage v ih 0.7*vd_reg vd v low-level input voltage v il - 0.20*vd_reg v high-level output voltage i o =2ma v oh 0.90*vd - v input leakage current i in -10 a input capacitance - 8 pf
8 ds786a2 cs4412a digital i/o pin characteristics the logic level for each input is set by its corresponding power supply and should not e xceed the maximum ratings. power supply pin number pin name i/o driver receiver vd 1 cnfg0 input - 2.5 v - 5.0 v 2 cnfg1 input - 2.5 v - 5.0 v 3 cnfg2 input - 2.5 v - 5.0 v 4 in1 input - 2.5 v - 5.0 v 5 in2 input - 2.5 v - 5.0 v 6 in3 input - 2.5 v - 5.0 v 7 in4 input - 2.5 v - 5.0 v 8rst12 input - 2.5 v - 5.0 v 9 lvd input - 2.5 v - 5.0 v 41 twr output 2.5 v - 5.0 v, open drain - 42 erruvte output 2.5 v - 5.0 v, open drain - 43 erroc12 output 2.5 v - 5.0 v, open drain - 44 erroc34 output 2.5 v - 5.0 v, open drain - 45 ramp input - 2.5 v - 5.0 v 46 rst34 input - 2.5 v - 5.0 v vp 35 out1 output 8 v - 18 v power mosfet - 32 out2 output 8 v - 18 v power mosfet - 29 out3 output 8 v - 18 v power mosfet - 26 out4 output 8 v - 18 v power mosfet - table 1. i/o power rails
ds786a2 9 cs4412a 3. typical connecti on diagrams 31 30 25 vp 36 vp vp vp 12 v d 0.1 f 10 f +3.3 v or +5.0 v in1 4 7 in4 in2 5 in3 6 24 ramp_cap ch1_pwm ch2_pwm out1 35 out2 32 out3 29 out4 26 ramp 45 cnfg2 3 cnfg1 2 cnfg0 1 lvd 9 system control logic 43 erroc12 erroc34 44 erruvte 42 twr 41 rst12 8 46 rst34 22 k ? vd 22 k ? 22 k ? 22 k ? 470 f 0.1 f 0.1 f 0.1 f 0.1 f 470 f +8 v to +18 v 22 28 34 37 38 39 40 33 p g n d pgn d pgn d p gn d pgn d pgn d pgn d pgn d gnd 13 gnd 16 gnd 17 gnd 14 gnd 15 vd_reg 11 0.1 f 10 f ocref 21 16.2 k gnd 18 gnd 19 gnd 47 gnd 48 27 pgn d 23 pgnd gnd 20 thermal pad gnd 10 vd * full-bridge output filter channel 2 audio output full-bridge output filter channel 1 audio output * since ramping is disabled for full- bridge applications, this capacitor can be omitted and ramp_cap can be connected directly to vp. ? connect lvd to : vd if vd = 5 v gnd if vd = 3.3 v figure 1. stereo full-bridge typical connection diagram cs4412a see section 5.1.1 for details. see section 4.2.1 for details. see figure 6 . see figure 6 .
10 ds786a2 cs4412a 31 30 25 vp 36 vp vp vp 12 vd 0.1 f 10 f +3.3 v or +5.0 v in1 4 7 in4 in2 5 in3 6 24 ramp_cap ch1_pwm ch2_pwm ch3_pwm out3 29 out4 26 out1 35 out2 32 system control logic 43 erroc12 erroc34 44 erruvte 42 twr 41 rst12 8 46 rst34 22 k ? vd 22 k ? 22 k ? 22 k ? ramp 45 cnfg2 3 cnfg1 2 cnfg0 1 lvd 9 full-bridge output filter half-bridge output filter half-bridge output filter 470 f 0.1 f 0.1 f 0.1 f 0.1 f 33 nf 470 f +8 v to +18 v 22 28 34 37 38 39 40 33 pg n d pgn d pgn d pgn d pgn d pgn d pgn d pgnd gnd 13 gnd 16 gnd 17 gnd 14 gnd 15 vd_reg 11 0.1 f 10 f ocref 21 16.2 k gnd 18 gnd 19 gnd 47 gnd 48 27 pg n d 23 pgnd gnd 20 thermal pad gnd 10 vd channel 2 audio output channel 1 audio output channel 3 audio output ? connect lvd to : vd if vd = 5 v gnd if vd = 3.3 v figure 2. 2.1 channel typical connection diagram cs4412a see section 5.1.1 for details. see figure 6 . see figure 5 . see figure 5 .
ds786a2 11 cs4412a 31 30 25 vp 36 vp vp vp 12 v d 0.1 f 10 f +3.3 v or +5.0 v 22 28 34 37 38 39 40 33 pgnd pgnd pg nd pgnd pgnd pgnd pgnd pgnd in1 4 gnd 13 gnd 16 gnd 17 gnd 14 gnd 15 vd_reg 11 0.1 f 10 f 7 in4 in2 5 in3 6 24 ramp_cap ocref 21 16.2 k gnd 18 gnd 19 gnd 47 gnd 48 27 p gnd 23 pgnd gnd 20 ch1_pwm ch2_pwm ch3_pwm ch4_pwm out1 35 out2 32 out3 29 out4 26 ramp 45 cnfg2 3 cnfg1 2 cnfg0 1 lvd 9 system control logic 43 erroc12 erroc34 44 erruvte 42 twr 41 rst12 8 46 rst34 22 k ? vd 22 k ? 22 k ? 22 k ? half-bridge output filter half-bridge output filter half-bridge output filter half-bridge output filter 470 f 0.1 f 0.1 f 0.1 f 0.1 f 33 nf 470 f +8 v to +18 v thermal pad gnd 10 channel 1 audio output channel 2 audio output channel 3 audio output channel 4 audio output vd ? connect lvd to : vd if vd = 5 v gnd if vd = 3.3 v figure 3. 4 channel half-bri dge typical connection diagram cs4412a see figure 5 . see figure 5 . see figure 5 . see figure 5 . see section 5.1.1 for details.
12 ds786a2 cs4412a +8 v to +18 v 31 30 25 v p 36 v p v p vp 12 v d 470 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 10 f +3.3 v or +5.0 v in1 4 7 in4 in2 5 in3 6 24 ramp_cap pwm out1 35 out2 32 system control logic 43 erroc12 erroc34 44 erruvte 42 twr 41 rst12 8 46 rst34 22 k ? vd 22 k ? 22 k ? ramp 45 cnfg2 3 cnfg1 2 cnfg0 1 lvd 9 470 f 22 28 34 37 38 39 40 33 pg n d p g n d p g n d pg n d p g n d pgn d p g n d pgnd vd_reg 11 0.1 f 10 f ocref 21 16.2 k 27 p g n d 23 pgn d thermal pad vd * * since ramping is disabled for full- bridge applications, this capacitor can be omitted and ramp_cap can be connected directly to vp. full-bridge output filter audio output ? connect lvd to : vd if vd = 5 v gnd if vd = 3.3 v gnd 13 gnd 16 gnd 17 gnd 14 gnd 15 gnd 18 gnd 19 gnd 47 gnd 48 gnd 20 gnd 10 out3 29 out4 26 see section 4.2.1 for details. cs4412a see figure 6 . see section 5.1.1 for details. figure 4. parallel full-bridge typical connection diagram
ds786a2 13 cs4412a 4. applications 4.1 overview the cs4412a is a high-efficiency power stage for di gital class-d amplifiers designed to be configured as four half-bridge channels, two half-bridge channels and one full-bridge channel, two full-bridge channels, or one parallel full- bridge channel. the cs4412a integrates on-chip over-current, under-vo ltage, over-temperature pr otection and error report- ing as well as a thermal wa rning indicator. the low r ds(on) outputs can source up to 2.5 a peak current, delivering 85% efficiency. this efficiency provides for a smaller device package, smaller powe r supplies, and no external heat sink. 4.2 reset and power-up reliable power-up can be accomplished by keeping the device in reset until the power supplies and config- uration pins are stable. it is also recommended that the rst12 and rst34 pins be activated if the voltage supplies drop below the recommended operating cond ition to prevent power- glitch rela ted issues. when the rst12 or rst34 are low, the corresponding channels of the cs4412a enter a low-power mode. all of the channels? internal states are reset, and th e corresponding power output pins are held in a high- impedance state. when rst12 or rst34 are high, the corresponding outputs begin normal operation ac- cording to the ramp, cnfg[2:0], and in1 - in4 pins. 4.2.1 pwm popguard transient control the cs4412a uses pwm popguard technology to minimize the effects of output transients during power- up and power-down for half-bridge configurations. this technique re duces the audio transients commonly produced by half-bridge, single-supply amplifiers wh en implemented with external dc-blocking capacitors connected in series with the audio outputs. warning: the popguard feature can not be used for the cs44 12a in applications where vp exceeds 12 v. doing so could result in permanent damage to the cs441 2a. the ramp pin must always be tied low in ap- plications where vp exceeds 12 v. when the device is configured for ramping (ramp set high) and rst12 or rst34 is set high, the corre- sponding power outputs will ramp-up to the bias point (vp/2). this gr adual voltage ramping allows time for the external dc-blocking capacito r to charge to the quiescent voltage, minimizing the power-up tran- sient. the corresponding outputs wi ll not begin normal operation until the ramp has reached the bias point. the time it takes to complete a ra mp-up sequence will vary slightly fr om the applied vp voltage; typical ramp-up speeds achieved with a 1000 f dc blocking capacitor are listed in table 2 . these times scale with the value of the capacitor. vp voltage typical ramp time* 8 v 2.20 seconds 12 v 1.25 seconds * with 1000 f dc blocking capacitor. table 2. typical ramp times for typical vp voltages
14 ds786a2 cs4412a when the device is configured for ramping (ramp set high) and rst12 or rst34 is set low, the corre- sponding outputs will begin to slowly ramp down from the bias point to pg nd, allowing the dc-blocking capacitor to discharge. the ramp feature is intended for use with half-bridge outputs. for ?2.1 channel? applications with stereo half-bridge and mono full-br idge (cnfg[2:0] = 001 or 101), the ramp will on ly be applied to out1 and out2 (the half-bridge channel s); out3 and out4 (the full- bridge channel) will not ramp. the ramp feature requires a 33 nf capacitor on the ramp_cap pin to vp. for applications that do not enable the ramping feature, ramp_cap can be connected directly to vp. it is not necessary to complete a ramp-up/down sequence before ramping up/down again. 4.2.2 initial pulse edge delay after rst12 or rst34 is released, the cs4412a continues to hold the corresponding power output pins in a high-impedance state until a pu lse edge is sensed on a corresponding pwm input pin. this is done to prevent a possible dc output cond ition on the speakers if the pwm inputs are not yet modulating im- mediately following the release of the corresponding re set signal. this initial transition delay is indepen- dent for each input/ou tput pin pair; each output corresponding to an inactive input will remain in a high- impedance state until its input rece ives a pulse edge even if other i nputs are activated. the pulse edge must be from a digital low state to a digital high st ate. once a pulse edge is detected, the corresponding output pin will activate and switch as dictated by the output mode c onfiguration described in section 4.3 on page 15 until either an error condition is dete cted or until its reset pin is set low. if the outputs are configured for ramping, the cs4412a w ill perform a ramp-up seq uence on out1/2 im- mediately following the release of rst12 and a ramp sequence on out3/4 immediately following the re- lease of rst34 . see section 4.2.1 on page 13 for more information on output ramping. if a pulse edge is detected on an input before the ramp-up sequence fi nishes on its corresponding output pin, the cs4412a continues the ramp sequence and begins normal outpu t operation immediately fo llowing its completion. if a pulse edge is not detected on an input by the time the ramp-up sequence has finished on its corre- sponding output pin, the output pi n is placed into and remains in a high-impedance state until a pulse edge is detected on the corresponding input. 4.2.3 recommended power-up sequence 1. turn on the system power. 2. hold rst12 and rst34 low until the power supply is stable. in this state, all associated outputs are held in a high-impedance state. 3. release rst12 and rst34 high. 4. start the pwm modulator output. 4.2.4 recommended power-down sequence 1. mute the logic-level pwm inputs present on in1 - in4 by applying 50% duty-cycle input signals. 2. hold rst12 and rst34 low. 3. power down the remainder of the system.
ds786a2 15 cs4412a 4.3 output mode configuration each outx pin will switch in associ ation with the corr esponding inx pin. for most configurations, outx will be non-inverted from inx; however, some inx pins can be configured for internal inversion to allow one pwm input to drive both the positive and negative sides of a full-bridge output. unused outx pins must have their corresponding inx pin tied to ground. table 3 shows the setting of the cnfg[2:0] inputs and the corresponding mode of operation. these pins should remain static during operation (rst12 or rst34 set high). in stereo half-bridge and mono full-bridge configur ations, the pwm popguard transient control only af- fects the two half-bridge outputs, out1 and out2. the full- bridge output will not ra mp regardless of the state of the ramp pin. see section 4.2.1 on page 13 for more details about pwm popguard transient con- trol. cnfg2 cnfg1 cnfg0 description necessary input connections 000 stereo full-bridge tied loads in1 must provide the pwm data for the first full-bridge. in2 must be inverted from in1 for full-bridge operation. in3 must provide the pwm data for the second full-bridge. in4 must be inverted from in3 for full-bridge operation. 001 stereo half-bridge & mono full-bridge tied loads* in1 must provide the pwm data for the first half-bridge. in2 must provide the pwm data for the second half-bridge. in3 must provide the pwm data for the mono full-bridge. in4 must be inverted from in3 for full-bridge operation. 010 mono parallel full- bridge tied load in1 must provide the pwm data for the mono full-bridge. in2 must be wired directly to in1 for parallel full-bridge operation. in3 must be inverted from in1 for parallel full-bridge operation. in4 must be wired to in3 for parallel full-bridge operation. 011 quad half-bridge tied loads in1 must provide the pwm data for the first half-bridge. in2 must provide the pwm data for the second half-bridge. in3 must provide the pwm data for the third half-bridge. in4 must provide the pwm data for the fourth half-bridge. 100 stereo full-bridge tied loads with inversion in1 must provide the pwm data for the first full-bridge. in2 must be wired to in1; the cs4412a will internally invert in2. in3 must provide the pwm data for the second full-bridge. in4 must be wired to in3; the cs4412a will internally invert in4. 101 stereo half-bridge & mono full-bridge tied loads with inversion* in1 must provide the pwm data for the first half-bridge. in2 must provide the pwm data for the second half-bridge. in3 must provide the pwm data for the mono full-bridge. in4 must be wired to in3; the cs4412a will internally invert in4. 110 mono parallel full- bridge tied load with inversion in1 must be provided for half-bridge operation. in2 must be wired to in1 for parallel full-bridge operation. in3 must be wired to in1; the cs4412a will internally invert in3. in4 must be wired to in1; the cs4412a will internally invert in4. 1 1 1 reserved the input connections are not applicable. * pwm popguard transient control only affects out1 and out2. table 3. output mode configuration options
16 ds786a2 cs4412a 4.4 output filters the filter placed after the pwm outputs can greatly affect the output performance. the filter not only reduces radiated emi (snubber filter) but also filters high frequency content from the switching output before going to the speaker (low-pass lc filter). 4.4.1 half-bridge output filter figure 5 shows the output filter for a half-bridge config uration. the transient-voltage suppression circuit (snubber circuit) is comprised of a capacitors (680 pf) and a resistor (5.6 ? , 1/8 w) and should be placed as close as possible to the corresponding pw m output pin to greatly reduce radiated emi. each output pin must be connected to two scho ttky diodes?one to ground and one to the vp supply. these diodes should be placed within 12 mm of the co rresponding outx pin. the requirements of this diode are: 1. rated i f (average rectifier forward current) is greater than or equal to 1.0 a. 2. support up to 80c of lead temperature with v f drop (forward voltage) less than or equal to 480 mv at the corresponding i f . 3. v r (reverse voltage) is greater than or equal to 20 v. the inductor, l1, and capacitor, c1, comprise the lo w-pass filter. along with the nominal load impedance of the speaker, these va lues set the cut-off frequency of the filter. table 4 shows the component values for l1 and c1 based on nominal speaker (load) impedance for a corner frequency (-3 db point) of approx- imately 35 khz. load l1 c1 4 ? 22 h 1.0 f 6 ? 33 h 0.68 f 8 ? 47 h 0.47 f table 4. low-pass filter components - half-bridge outx 680 pf c1 5.6 ? l1 c2 +- vp *diode is rohm rb160m-30 or equivalent figure 5. output filter - half-bridge
ds786a2 17 cs4412a c2 is the dc-blocking capacitor. table 5 shows the component values for c2 based on corner frequency (-3 db point) and a nominal speaker (load) impedances of 4 ?, 6 ?, and 8 ? . this capacitor should also be chosen to have a ripple curr ent rating above the amount of cu rrent that will pa ssed through it. load corner frequency c2 4 ? 40 hz 1000 f 58 hz 680 f 120 hz 330 f 6 ? 39 hz 680 f 68 hz 390 f 120 hz 220 f 8 ? 42 hz 470 f 60 hz 330 f 110 hz 180 f table 5. dc-blocking capacitors values - half-bridge
18 ds786a2 cs4412a 4.4.2 full-bridge output filter (stereo or parallel) figure 6 shows the output filter for a full-bridge config uration. the transient-vol tage suppression circuit (snubber circuit) is comprised of a capacitor (680 pf) and a resistor (5.6 ? ) on each output pin and should be placed as close as possible to the corresponding pwm output pins to greatly reduce radiated emi. the inductors, l1 and l2, and capacitor, c1, comprise t he low-pass filter. along with the nominal load imped- ance of the speaker, t hese values set the cutoff frequency of the filter. table 6 shows the component val- ues based on nominal speaker (load) impedance for a corner frequency (-3 db point) of approximately 35 khz. each output pin must be connected to two scho ttky diodes?one to ground and one to the vp supply. these diodes should be placed within 12 mm of the co rresponding outx pin. the requirements of this diode are: 1. rated i f (average rectifier forward current) is greater than or equal to 1.0 a. 2. support up to 80c of lead temperature with v f drop (forward voltage) less than or equal to 480 mv at the corresponding i f . 3. v r (reverse voltage) is greater than or equal to 20 v. load l1, l2 c1 4 ? 10 h 1.0 f 6 ? 15 h 0.47 f 8 ? 22 h 0.47 f table 6. low-pass filter components - full-bridge figure 6. output filter - full-bridge outx+ outx- c1 l1 l2 *diode is rohm rb160m-30 or equivalent vp vp 680 pf 5.6 ? 680 pf 5.6 ?
ds786a2 19 cs4412a 4.5 device protection and error reporting the cs4412a has built-in protection circuitry for over-current, under-vo ltage, and therma l warning/over- load conditions. the levels of the over-current error, thermal error, and vp under-voltage trigger points are listed in the pwm power output characteristics table on page 6 . automatic shut-down occurs when- ever any of these preset thresholds, ot her than thermal warning, are crossed. each error and warning pin implements an active-low open-drain driver and requires an external 22 k ? pull-up resistor for proper operation. 4.5.1 over-current protection an over-current error condition occurs if the peak output current exceeds the over-current error trigger point. over-current errors for out1/2 and out3/4 are reported on the erroc12 and erroc34 pins, respectively. the power output of the channel that is reporting the over-current condition will be set to high-impedance until the error condition has been remo ved and the reset signal for that channel has been toggled from low to high. 4.5.2 thermal warning, thermal error, and under-voltage error table 8 shows the behavior of the twr and erruvte pins. when the junction temperature exceeds the junction thermal warnin g trigger point, the twr pin is set low. if the junction temperature continues to in- crease beyond the junction thermal error trigger point, the erruvte pin will be set low. if the voltage on vp falls below the vp under-volt age error trigger point, erruvte will be set low. when the thermal error or vp under-voltage trigger poin t is crossed, all power ou tputs will be set in a high- impedance state until the error condition has been removed and both the rst12 and rst34 signals have been toggled from low to high. errocxy reported condition 0 over-current error on channel x or channel y 1 operating current of channel x and y within allowable limits table 7. over-current error conditions twr erruvte reported condition 0 0 thermal warning and thermal error and/or under-voltage error 0 1 thermal warning only 1 0 under-voltage error 1 1 junction temperature and vp voltage within normal limits table 8. thermal and under-voltage error conditions
20 ds786a2 cs4412a 5. power supply, grounding, and pcb layout 5.1 power supply and grounding the cs4412a requires careful attention to power supply and grounding arrangements if its potential perfor- mance is to be realized. extensive use of power and ground pl anes, ground plane fill in unused areas, and surface mount decoupling capacitors are recommended. it is necessary to decoup le the power supply by placing capacitors directly between the power and ground of the cs4412a. decouplin g capacitors should be as close to the pins of the cs4412a as possible. the lowest value ceramic ca pacitor should be closest to the pin and should be mounted on the same side of the board as the cs4 412a to minimize inductance effects. the crd4412a reference design demonstrates the opti mum layout and power supply arrangements. 5.1.1 integrated vd regulator the cs4412a includes an internal linear regulator to provide a fixed 2.5 v supply from the vd supply volt- age for its internal digital logic. the lvd pin must be set to indicate the voltage present on the vd pin as shown in table 9 below. table 9. power supply configuration and settings the output of the digital regulator is presented on th e vd_reg pin and may be used to provide an exter- nal device with up to 3ma of current at its nominal output voltage of 2.5 v . if a nominal supply voltage of 2.5 v is used as the vd supply (see the recommended operating condi- tions table on page 5 ), the vd and vd_reg must be connected to the vd supply source. in this config- uration, the internal regulator is bypassed and the exte rnal supply source is used to directly drive the internal digital logic. 5.2 qfn thermal pad the cs4412a is available in a compact qfn package. the underside of the qfn package reveals a large metal pad that serves as a thermal relief to provide fo r maximum heat dissipation. this pad must mate with an equally dimensioned copper pad on the pcb and must be electrically connected to ground. a series of thermal vias should be used to connect this copper pa d to one or more larger ground planes on other pcb layers; the copper in thes e ground planes will act as a heat sink for the cs4412a. the crd4412a reference design demonstrates the optimum thermal pad and via configuration. vd connection vd_reg connection lvd connection 5 v supply bypass capacitors only vd 3.3 v supply bypass capacitors only gnd 2.5 v supply vd and bypass capacitors gnd
ds786a2 21 cs4412a 6. parameter definitions dynamic range (dyr) the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth, typically 20 hz to 20 kh z. dynamic range is a signal-to-noise ratio measurement over the spec- ified band width made with a -60 dbfs signal; then, 60 db is added to the resulting measurement to refer the measurement to full-scale. this technique ensures that the distortion components are below the noise level and do not effect the measurement. this meas urement technique has been accepted by the audio engineering society, aes17-1991, and the electronic industries associat ion of japan, eiaj cp-307. ex- pressed in decibels. total harmonic distortion + noise (thd+n) the ratio of the rms value of the si gnal to the rms sum of all other sp ectral components over the specified band width (typically 10 hz to 20 khz), including di stortion components. expressed in decibels. measured at -1 and -20 dbfs as sugg ested in aes17-1991 annex a.
22 ds786a2 cs4412a 7. package dimensions notes: 1. dimensioning and tolerance per asme y4.5m - 1994. 2. dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm from the terminal tip. inches millimeters note dim min nom max min nom max a -- -- 0.0354 -- -- 0.90 1 a1 0.0000 -- 0.0020 0.00 -- 0.05 1 b 0.0118 0.0138 0.0157 0.30 0.35 0.40 1 , 2 d 0.3543 bsc 9.00 bsc 1 d2 0.2618 0.2677 0.2736 6.65 6.80 6.95 1 e 0.3543 bsc 9.00 bsc 1 e2 0.2618 0.2677 0.2736 6.65 6.80 6.95 1 e 0.0256 bsc 0.65 bsc 1 l 0.0177 0.0217 0.0276 0.45 0.55 0.70 1 jedec #: mo-220 controlling dimension is millimeters. side view a1 bottom view top view a pin #1 id d e d2 l b e pin #1 id e2 48l qfn (9 9 mm body) package drawing
ds786a2 23 cs4412a 8. thermal characteristics 8.1 thermal flag this device is designed to have the metal flag on the bo ttom of the device soldered directly to a metal plane on the pcb. to enhance the thermal dissipation capabilities of the syst em, this metal plane should be cou- pled with vias to a large metal plane on the backside (and inner ground layer, if applicable) of the pcb. in either case, it is beneficial to use copper fill in any unused regions inside th e pcb layout, especially those immediately surrounding the cs4412a. in addition to im proving in electrical performance, this practice also aids in heat dissipation. the heat dissipation capabilit y required of the metal plane for a gi ven output power can be calculated as follows: ca = [(t j(max) - t a ) / p d ] - jc where, ca = thermal resistance of the metal plane in c/watt t j(max) = maximum rated operating junction temperature in c, equal to 150c t a = ambient temperature in c p d = rms power dissipation of the device, equal to 0.15*p in,rms or 0.177*p out,rms (assuming 85% effi- ciency) jc = junction-to-case thermal resistance of the device in c/watt 9. ordering information 10.revision history parameter symbol min typ max units junction to case thermal impedance jc -1 -c/watt product description package pb-free grade temp range container order# cs4412a 30 w quad half-bridge digital amplifier power stage 48-qfn yes commercial -10c to +70c rail cs4412a-cnz tape and reel cs4412a-cnzr crd4412a 4 layer / 3oz. copper reference design daughter card - - - - - crd4412a CRD4525-Q1 4 layer / 1oz. copper reference design main board - - - - - CRD4525-Q1 release changes a1 initial release a2 the following items were update: ?pwm power output characteristics? on page 6 section 4.4.1 ?half-bridge output filter? on page 16 section 4.4.2 ?full-bridge output f ilter (stereo or parallel)? on page 18 section 8.1 ?thermal flag? on page 23 section 9. ?ordering information? on page 23
24 ds786a2 cs4412a contacting cirrus logic support for all product questions and inquiries, contact a cirrus logic sales representative. to find one nearest you, go to www.cirrus.com. important notice ?advance? product information describes products that are in development and subject to development changes. cirrus logic, inc. and its subsidiaries (?cirrus?) be- lieve that the information contained in this document is accurate and reliable. however, the information is subject to change w ithout notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information t o verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limit ation of liability. no responsibility is assumed by cirrus fo r the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, co pyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information contained herein and gives conse nt for copies to be made of the infor- mation only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this conse nt does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semi conductor products may involve po tential risks of death, perso nal injury, or severe prop- erty or environmental damage (? critical applications?). cirrus products are not designed, authorized or warranted for use in products surgically implanted into the body, automotive safety or security devices, life su pport products or other crit- ical applications. inclus ion of cirrus products in such appl ications is understood to be full y at the customer?s risk and cir- rus disclaims and makes no warranty, expres s, statutory or implied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or custom- er?s customer uses or permits the use of cirrus products in cr itical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any a nd all liability, including at- torneys? fees and costs, that may result fr om or arise in connection with these uses. cirrus logic, cirrus, the cirrus logic logo designs, and popguard are trademarks of cirrus logic, inc. all other brand and prod uct names in this document may be trademarks or service marks of their respective owners.

▲Up To Search▲

Price & Availability of CRD4525-Q1

	To Download CRD4525-Q1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .